When using the Arria® 10 PCIE* IP core, does assertion of a correctable error during speed change from Gen3 x1/x2 to Gen1 or Gen2 mean the link is unreliable? - When using the Arria® 10 PCIE* IP core, does assertion of a correctable error during speed change from Gen3 x1/x2 to Gen1 or Gen2 mean the link is unreliable? Description You may observe a correctable error assertion during the Recovery state when the Arria® 10 PCIE* IP core changes the speed from Gen3 x1/x2 to Gen1 or Gen2. The corretable error during the speed change does not indicate low link quality and can be ignored. Resolution No workaround or fix is required for this problem. Once the error is cleared by system software, it should remain deasserted. Custom Fields values: ['novalue'] Troubleshooting FB: 326165; True ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix No plan to fix ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']