Extracting FPGA architecture file from Chip Planner - Extracting FPGA architecture file from Chip Planner I am playing around with Agilex device(AGRB014R24A3E3VR0). I found that the device looks really regular; the left three clock sectors are almost identical and the right three clock sectors are almost identical. Is there any way to extract resource composition from Chip Planner? For instance, I noticed that there's "Find" functionality that if I try to find "LAB*", it outputs all the LABs. I wonder if there's way to export this find output as a file. Also, I guess there should be some hardware architecture file for all the devices. If I can extract resource distribution for a certain device from such file, that would be helpful too. Thanks. Replies: Re: Extracting FPGA architecture file from Chip Planner @Ash_R_Intel Thanks for the reply. It's sad that what we can easily get from the gui isn't available as a script ;-( The feature should be really useful to analyze the device. Replies: Re: Extracting FPGA architecture file from Chip Planner Sorry, there isn't any such option available to export the information from Chipplanner. Regards Replies: Re: Extracting FPGA architecture file from Chip Planner https://www.intel.com/content/www/us/en/docs/programmable/683641/22-3/finding-design-elements-in-the-chip-planner.html I found the "Find" functionality above is useful. Is there any way to export the results to a file and run the "Find" command in tcl? Replies: Re: Extracting FPGA architecture file from Chip Planner Thanks for the reply. My question was, how can we extract resource composition of a specific device . Below is a screenshot of a sample Agilex 7 series device, and the resource columns(from left to right) are HSSI AIBND RX, LAB, LAB, LAB, LAB, M20K, LAB, and so on. I wonder if there's a way to extract this info without hand-extracting from the Chip Planner. Replies: Re: Extracting FPGA architecture file from Chip Planner Hi, The general architecture description for a device is provided in the documentation for the device and there is a whole bunch of them based on which type of resource you are looking for. For Agilex 7, please refer to the following documentation page: https://www.intel.in/content/www/in/en/products/details/fpga/agilex/7/docs.html Feel free to apply filter based on the area of documentation. You can find information on where each of you design block is placed from the _fit.rpt. Regards