Creonic DVB-S2 Demodulator - The Creonic DVB-S2 high performance demodulator IP core performs all tasks of an inner receiver. Its output perfectly fits the DVB-S2 forward error correction IP core from Creonic that implements… Creonic is the ISO 9001:2015 certified leader in ready-for-use IP cores, offering a rich services and product portfolio for wired, wireless, fiber, and free-space optical communications. Covering… Intel® Arria® 10 SX SoC FPGA Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel® MAX® 10 FPGA Arria® V GZ FPGA Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series MAX® V CPLD Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Arria® V SX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 SX SoC FPGA Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Cyclone® V GT FPGA Intel® Arria® 10 GT FPGA Arria® V ST SoC FPGA Intel® Arria® 10 GX FPGA Intel® Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel® Stratix® 10 GX FPGA Arria® V GT FPGA Intel® Cyclone® 10 LP FPGA Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel® Cyclone® 10 GX FPGA Intel® Stratix® 10 AX SoC FPGA Stratix® III FPGA DVB-S2 (Digital Video Broadcast – Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites. It was published in 2005, being the first standard of the second generation DVB standards (DVB-S2/DVB-T2/DVB-C2). Because of its capacity-approaching forward error correction, today DVB-S2 is the de-facto standard in satellite communication and other applications. The Creonic DVB-S2 high performance demodulator IP core performs all tasks of an inner receiver. Its output perfectly fits the DVB-S2 forward error correction IP core from Creonic that implements LDPC and BCH decoding. Aerospace Wireless Creonic DVB-S2 Demodulator Key Features Compliant with ETSI 302 307 V1.2.1 (2009-08) (DVB-S2) Supports ACM, VCM, CCM mode for broadcasting Offering Brief No No No No C/C++ Verilog VHDL Intel® Arria® 10 SX SoC FPGA Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel® MAX® 10 FPGA Arria® V GZ FPGA Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series MAX® V CPLD Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Arria® V SX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 SX SoC FPGA Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Cyclone® V GT FPGA Intel® Arria® 10 GT FPGA Arria® V ST SoC FPGA Intel® Arria® 10 GX FPGA Intel® Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel® Stratix® 10 GX FPGA Arria® V GT FPGA Intel® Cyclone® 10 LP FPGA Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel® Cyclone® 10 GX FPGA Intel® Stratix® 10 AX SoC FPGA Stratix® III FPGA No Yes 22.4.0 Offering Brief Production a1JUi0000049U8hMAE What's Included Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model Ordering Information Creonic DVB-S2 Demodulator a1JUi0000049U8hMAE Production Intellectual Property (IP) Communication a1MUi00000BO8rZMAT a1MUi00000BO8rZMAT Select 2025-11-21T23:26:28.000+0000 The Creonic DVB-S2 high performance demodulator IP core performs all tasks of an inner receiver. Its output perfectly fits the DVB-S2 forward error correction IP core from Creonic that implements LDPC and BCH decoding. Partner Solutions