Inferring Simple dual-port RAM with write enable & read enable - Inferring Simple dual-port RAM with write enable & read enable I compiled the project with Single-clock simple dual-port RAM with write & read enable like attached quartus project. But the compiler output the warning like below. Warning (276027): Inferred dual-clock RAM node "FIR_x2:u_FIR_x2_L_960|DATA_BUFFER:u_DATA_BUFFER|simple_dual_port_ram:u_simple_dual_port_ram|ram_rtl_0" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design. I found that the warning is diappeared when I changed the code without read enable (re). Quartus Prime infers the RAM with write & read enable as dual-clock? If there are solutions to infer this RAM without warning, please teach me how to. Thanks, AUDIY Replies: Re: Inferring Simple dual-port RAM with write enable & read enable I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com’ , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Replies: Re: Inferring Simple dual-port RAM with write enable & read enable Hi, Thank you for your solution and I checked the warning is removed. I designed this project that when (re) is toggled (1'b1 -> 1'b0) when written address is the same as read address. So I think this warning is no-problem actually but I keep in mind this solution. Thanks, AUDIY. Replies: Re: Inferring Simple dual-port RAM with write enable & read enable Hi, read-during-write behaviour is only critical for same address applied to read andwrite port simultaneously. MAX10 M9K as well as e.g. Arria 10 M20K support "old-data" or "don't care" mode for single clock DP RAM. "new data" isn't supported and needs to be emulated by additional registers and read data mux if required in your application. I don't recognize at first sight if read-during-write behaviour is relevant for you application. It can be best checked in a simulation. My previous post needs to be corrected. It's not a problem of missing rden port, M9K actually has a rden port and the device handbook suggests to use if for power saving. Problem is the doubled connection of rden in your code always @ (posedge wclk) begin if (we) begin ram[waddr] <= wdata; end if (re) begin r_rdata_1P <= ram[raddr]; r_rdata_2P <= r_rdata_1P; end end generate if (OUTPUT_REG == "TRUE") assign rdata = r_rdata_2P; else assign rdata = r_rdata_1P; endgenerate Only the second assignment should be gated by (re). Doing so stops dual-clock RAM inference and removes the warnigs. Replies: Re: Inferring Simple dual-port RAM with write enable & read enable Dear FvM, Please would you tell me your experience? When the read-during-write behavior is occured (in this situation, write address & read address are NOT the same), do you know how the infered RAM to behave? Thanks, AUDIY Replies: Re: Inferring Simple dual-port RAM with write enable & read enable Thank you for your answer. I try changing design you recommend. Thanks, AUDIY Replies: Re: Inferring Simple dual-port RAM with write enable & read enable Intel block RAM doesn't provide read enable, it's apparently emulated by clock enable in your design, respectively needing two clocks. According to my experience, RAM read enable is rarely necessary in designs, the function can be achieved by other means like separate output register.