Which specific PCIe (PCI* Express) Hard IP block can be used for CvP (Configuration via Protocol) application? - Which specific PCIe (PCI* Express) Hard IP block can be used for CvP (Configuration via Protocol) application? Description A CvP system typically comprises an FPGA, a PCIe* host, and a configuration device. For devices that support two or more PCIe Hard IP blocks on the left, the user needs to define which block can be used for the CvP application. Taking the Agilex™ 7 FPGAs Device as an example, the original description in 1.2. CvP System of Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide is: The FPGA connects to the configuration device using the Active Serial x4 (fast mode) configuration scheme. For devices that support only one PCIe Hard IP block on the left, the lower left PCIe Hard IP block is used for CvP application. For devices that support two or more PCIe Hard IP block on the left, CvP application can use either top or bottom of the PCIe Hard IP blocks on the left side. PCIe Hard IP blocks that are not used for CvP can be used for PCIe application. Resolution To clarify the PCIe Hard IP block description, the 1.2. CvP System of Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide will be updated with the following statements : The FPGA connects to the configuration device using the Active Serial x4 (fast mode) configuration scheme. The PCIe Hard IP block located near the SDM block are on the left side and can be used for CvP applications. However, only one PCIe Hard IP block can be used for CvP application at one time. PCIe Hard IP blocks that are not used for CvP can be used for PCIe application. Related Articles Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Custom Fields values: ['novalue'] Troubleshooting 15017368597 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1 22.4 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']