Why do I see the hold timing violation in DCP1.2 OpenCL BSP design? - Why do I see the hold timing violation in DCP1.2 OpenCL BSP design? Description You may see a small hold timing violation when you compile a DCP1.2 OpenCL BSP design. Resolution This hold timing violation does not cause any functional issue on DCP1.2 OpenCL BSP design. This problem has been fixed in DCP 1.2.1 OpenCL BSP design. Custom Fields values: ['novalue'] Troubleshooting 1507078259 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 17.1.2 ['Arria® 10 FPGAs and SoCs'] ['HLD Tools OpenCL'] ['novalue'] ['novalue']