about DDR3 init ,god please - about DDR3 init ,god please hello,every god!! I have been debugging DDR3 recently using the Altera CycloneVsoc development board. My DDR3 timing display reset signal did not raise, but my DDR3 initialization signal was successful, which is inconsistent with my DDR3 simulation modelsim tell me ,reset and clk_we will be high before init_done however,signaltap tell me ini_done ,resetn and cke is low Which God can tell me,thanks very mach!! Replies: Re: about DDR3 init ,god please I actually tested DDR3_resetn and DDR3_cke on the oscilloscope, and these two signals were indeed DDR3_resetn pulled up first, and DDR3_cke pulled up after 500us. However, my DDR3 still fails to initialize. Do you think all DDR3 signals need to be of equal length, because my cas/ras and other control signals are not as long as the data signal Replies: Re: about DDR3 init ,god please i see! so, Can I use some methods to see these signals from the signalnap? Replies: Re: about DDR3 init ,god please Hi, Do you have any further question in this case? Regards, Adzim Replies: Re: about DDR3 init ,god please Hi I think the signal tap cannot capture the signal from mem* conduit since it connected to the memory component. Therefore, you may not see the signals are triggering in the signal tap. You may refer to the simulation test run to observe these signals behavior. I think the memory datasheet may has some description in the power up and initialization of memory section that you can refer to. Regards, Adzim