Introduction to the Altera® FPGA R-Tile - 35 Minutes Select Altera® Agilex ® 7 FPGAs are packaged with Altera's R-Tile transceiver tile, which implements the PCI Express* standard Gen3, Gen4 and Gen5. This training is the first step in learning how to build a high-speed interface using the R-Tile. You will begin by learning about Altera's Embedded Multi-Die Interconnect Bridge (EMIB) technology that makes packaging the R-Tile with a high-speed FPGA fabric possible. You will then be introduced to the architecture and key features of the R-Tile including its operating modes and features such as Multilink Capability, TLP Bypass and Configuration via Protocol. The class will end describing the advanced features of the R-tile used in multi-function applications and systems employing virtualization. Course Objectives At course completion, you will be able to: Describe the functional blocks found in the R-Tile Describe the many options for customizing the R-Tile architecture for use in a system Describe R-tile system-level connections and behavior Describe R-tile features used in multi-function applications and virtual systems such single-root IO virtualization (SR-IOV) and Altera® Scalable VIO Skills Required General understanding of transceivers General understanding of PCI Express* Protocol If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ORTILE. FPGA_ORTILE. <p>Introduction to the Altera FPGA R-Tile</p>