Introduction to the Triple-Speed Ethernet FPGA IP - 25 Minutes The Triple-Speed Ethernet FPGA IP provides a customizable and flexible solution for implementing Ethernet media access control (MAC) and/or physical coding sublayer (PCS) layers. This online course will introduce you to the features and interfaces of the Triple-Speed Ethernet FPGA IP when targeting Altera® FPGAs using the Quartus® Prime software. Course Objectives At course completion, you will be able to: Describe the features and functionality Triple-Speed Ethernet FPGA IP Describe the interface found on the Triple-Speed Ethernet FPGA IP Skills Required Skills Required Understanding of the Ethernet technology specifications Familiarity with common high-speed transceiver architecture or viewing the following course: Transceiver Basics Familiarity with FPGA/CPLD design flow Familiarity with the Quartus Prime Pro design software Familiarity with Platform Designer If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OTSE1116. FPGA_OTSE1116. <p>Introduction to the Triple-Speed Ethernet FPGA IP</p>