Why does the Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express design example targeting the Intel Agilex® 7 FPGA show minimum pulse width violations? - Why does the Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express design example targeting the Intel Agilex® 7 FPGA show minimum pulse width violations? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2 and earlier, you might see minimum pulse width violations when using the design example for the Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express targeting the Intel Agilex® 7 FPGA. Resolution This problem is fixed starting with the Intel® Quartus® Prime Edition Software 21.3. Custom Fields values: ['novalue'] Troubleshooting 1509272964 False ['Example Application Avalon-Streaming Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 21.2 ['Agilex™ 7 FPGA F-Series'] ['novalue'] ['novalue'] ['novalue']