Avalon Streaming Dual Clock FIFO - Avalon Streaming Dual Clock FIFO Hi, I am trying to connect the AV DC FIFO as followed: The idea being that the main clock is running at 100MHz and is connected to the mSGDMA which reads from the FIFO, and iopll is outputting a 200MHz clock and is connected to the oscillator which writes to the FIFO. The above design compiles, but on boot I am given this error: ..Error sending bitstream! Command 'load' failed: Error -110 FPGA not ready. Bridge reset aborted! Note that this design works when there is no PLL , and everything is clocked from the same source (although this causes boot to take a long time). I have looked through the docs here however these docs seems not to match the IP interfaces. The docs here here seem to match but don't explain the interface. Could someone help point me in the correct direction? Thanks! Replies: Re: Avalon Streaming Dual Clock FIFO Hi, Understood that. Could you try to use the simple adapter ST handshake clock crosser under the bridges and adapters section? I think you're connecting it correctly previously. Instead of using dual clock fifo under on-chip memory section, as it's embedded peripheral I'm not sure is there anything needs to take note when using it. Regarding why booting slow when using 200mhz, you need to open a new thread target pcie to get the related pcie expert helps. Thanks, Regards, Sheng Replies: Re: Avalon Streaming Dual Clock FIFO Because mSGDMA is connected to HPS, which operates at a slower rate (100MHz). Eventually, we want to clock the oscillator at 300+ MHz, so we cannot feed this to mSGDMA, right? Replies: Re: Avalon Streaming Dual Clock FIFO Hi, May I know why at the beigning you feed the oscillator to 200mhz while msgdma to 100mhz? Is that to increase the booting speed? Seems like even feed all peripherals to 200mhz, the booting speed even slower as you mentioned. Your ultimate goal is to increase the booting speed? Thanks, Regards, Sheng Replies: Re: Avalon Streaming Dual Clock FIFO Main clock(50mhz) -> pll (200mhz) -> all peripherals did work! Thanks. However - the system boot is now much much slower. Maybe 10x slower. Do you know why this could be?? Many thanks. Replies: Re: Avalon Streaming Dual Clock FIFO Hi, Could you try test case below: Test1: Main clock(50mhz) -> pll (50mhz) -> all peripherals Test2: Main clock(50mhz) -> pll (100/200mhz) -> all peripherals Are both tests pass? Replies: Re: Avalon Streaming Dual Clock FIFO Hi, You mean you change the pll frequency to 50mhz or connect the oscillator to 50mhz? Does the device got 100mhz clock? Thanks, Regards, Sheng Replies: Re: Avalon Streaming Dual Clock FIFO Hi @ShengN_Intel , I can confirm that with the 50MHz clock this design works: With a verilog defined for the clock: ... // Qsys Top module assign sys_clk_50 = REFCLK_50; qsys_top soc_inst ( ... .clk_50_clk (sys_clk_50), ... ); ... I would note, however, that I do not have another clock going faster than my main system clock to test with - which is why my application will be relying on a PLL. What would you suggest to try now? Replies: Re: Avalon Streaming Dual Clock FIFO Hi, Understood that. Could you replace that iopll with clock source to check whether the problem is on the pll? If the problem is on pll, then would need pll folk to look into this. Thanks, Regards, Sheng Replies: Re: Avalon Streaming Dual Clock FIFO The issue is that during boot I cannot actually load the initial design onto the fpga, and so cannot use signal tap! Replies: Re: Avalon Streaming Dual Clock FIFO Hi, I just realised you use st dual clock fifo ip already, that ip will handle cdc already. Not sure is that the lock reset problem of the pll, could you signal tap the pll to the osillator? Also try replace that iopll with another clock source does the problem resolved? Thanks, Regards, Sheng Replies: Re: Avalon Streaming Dual Clock FIFO Hi @ShengN_Intel Many thanks for the reply! Could you tell me, is this the only Avalon® -ST Streaming Pipeline Stage IP Docs? In fact, if the design you suggest is this one: Am I correct? If so would I be correct to say that if this IP would be placed in between the oscillator and the FIFO, then the read speed would stay at 100 MHz? Many thanks! Replies: Re: Avalon Streaming Dual Clock FIFO Hi there @ShengN_Intel Thanks for this suggestion! Do you know where the docs are for this IP - all I can seem to find is this ? May I ask if this is to be used as followed: And if so - how does this IP manage data transfer? Replies: Re: Avalon Streaming Dual Clock FIFO Hi, Another one will be using Avalon Streaming Handshake Clock Crosser IP. Replies: Re: Avalon Streaming Dual Clock FIFO Hi, Seems like a cdc problem where msgdma read from fifo at 100mhz but oscillator write to fifo at 200mhz. If you make the clock frequency same does the problem resolved? If yes, I would suggest you to add one Avalon® -ST Streaming Pipeline Stage IP in between the msgdma and fifo reading to increase the reading frequency to 200mhz Thanks, Regards, Sheng