Why does EMIF for HPS LPDDR4 fail calibration on the Agilex™ 5 FPGA and SoC FPGA? - Why does EMIF for HPS LPDDR4 fail calibration on the Agilex™ 5 FPGA and SoC FPGA? Description In the Quartus® Prime Pro Edition Software 24.3, when configuring the Agilex™ 5 FPGAs and SoC FPGAs with the EMIF for HPS IP and LPDDR4 device implemented as dual rank (2 chip selects), dual channels (i.e., 4 dies each being 16 Gbit in density), calibration can fail. Resolution Please download the Quartus® Prime Pro Edition Software 24.3 patch 0.11 for a fix. This issue is planned to be fixed in a later Quartus® Prime Pro Edition Software release. quartus-24.3-0.11-windows.exe quartus-24.3-0.11-linux.run quartus-24.3-0.11-readme.txt Custom Fields values: ['novalue'] Errata 15016555812 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.3 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']