Fitter Error when using PCIE HIP Channels for PIPE design - Fitter Error when using PCIE HIP Channels for PIPE design Description When generating Gen3x8 PIPE's design with -2/-3 speed grade device and assign the pin locations of tx/rx to PCIE HIP's placement, there will be fit error reported like below: Error(18510): PIPE master channel < ovSOFTPCIE_TxP[4] > can't be placed at the HIP channel location < PIN_BF49 > due to timing requirement. Either change the master channel to a different index to avoid HIP channel locations, or change master channel location to avoid HIP channel locations, or change speed grade to 1. This error will be reported when using QuartusII® 17.0/17.1 build version and target device is -2/-3 speed grade. Resolution For 17.0/17.1 build version, please change device speed grade to 1. This error was fixed by QuartusII® 18.1 and above version. Recommend upgrade QII version to 18.1 and above for Stratix10® series PIPE design. Custom Fields values: ['novalue'] Troubleshooting FB: 1408206073; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 17.1 ['Stratix® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']