How do I implement a "One 18 x 19 Multiplication Summed with 36-Bit Input Mode" DSP function in an Intel® Arria® 10 device? - How do I implement a "One 18 x 19 Multiplication Summed with 36-Bit Input Mode" DSP function in an Intel® Arria® 10 device? Description To implement this (or other) advanced Intel® Arria® 10 FPGA digital signal processing (DSP) configuration, use the HDL templates available in the Quartus® II software. Resolution For a list of available templates, follow these steps: Right-click in a VHDL or Verilog HDL file, and select Insert Template . Select VHDL or Verilog HDL, then select Full Designs > Arithmetic > DSP Features > DSP Features for 20-nm device. Custom Fields values: ['novalue'] Troubleshooting - False ['novalue'] ['novalue'] novalue novalue ['Arria® 10 FPGAs and SoCs', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']