Why does the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP core forward RX truncated invalid frames to user logic? - Why does the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP core forward RX truncated invalid frames to user logic? Description The v18.0 Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP core has a problem with oversized frame stripping. When the RX MAC receives a frame size >= 65536, and enforce_max_frame_size is enabled, the frame output from RX MAC to user logic will be truncated to frame size specified by max_rx_frame_size settings, and a second invalid frame will output from the RX MAC to user logic starting from 65536-byte to the end of the super large frame. Resolution No workaround to this problem currently exists. This problem is scheduled to be fixed in a future version of the Intel® Quartus® Prime Edition Software. Custom Fields values: ['novalue'] Troubleshooting FB: 555284; True ['Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 18.0 ['Stratix® 10 FPGAs and SoCs', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']