Why does the simulation of my Dual Port RAM Intel® FPGA IP have incorrect read-during-write behavior? - Why does the simulation of my Dual Port RAM Intel® FPGA IP have incorrect read-during-write behavior? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software, you might see incorrect old data behaviour for read-during-write operations when new data is expected. This problem only affects the simulation behaviour for Dual Port RAM Intel® FPGA IP with the following configuration for Intel® Stratix® 10 devices and Intel Agilex® devices : RAM block type is MLAB Read address is unregistered Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3. Custom Fields values: ['novalue'] Troubleshooting 1509433779 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 21.2 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']