Due to a problem in the Quartus® II software version 13.1 and earlier, you may see the following Design Assistant critical warnings when you use the altlvds_rx IP. - Due to a problem in the Quartus® II software version 13.1 and earlier, you may see the following Design Assistant critical warnings when you use the altlvds_rx IP. Description Due to a problem in the Quartus® II software version 13.1 and earlier, you may see the following Design Assistant critical warnings when you use the altlvds_rx IP: Critical Warning (308024): (High) Rule R101: Combinational logic used as a reset signal should be synchronized. Found 4 node(s) related to this rule. Critical Warning (308012): Node "altlvds_rx:ALTLVDS_RX_component|test_lvds_rx:auto_generated|wire_dffe15_clrn~0" Critical Warning (308012): Node "altlvds_rx:ALTLVDS_RX_component|test_lvds_rx:auto_generated|wire_dffe36_clrn~0" Resolution This R101 violation critical warning can be safely ignored because the inputs to the combinational logic will not produce a hazardous glitch for the reset signal. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Reset'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']