Why doesn't the Receiver Precision Time Protocol (PTP) Ready signal (o_sl_rx_ptp_ready) assert after completing the reset and calibration sequence in 10G/25G PTP variants of the E-Tile Hard IP for Ethernet Intel® FPGA IP Core? - Why doesn't the Receiver Precision Time Protocol (PTP) Ready signal (o_sl_rx_ptp_ready) assert after completing the reset and calibration sequence in 10G/25G PTP variants of the E-Tile Hard IP for Ethernet Intel® FPGA IP Core? Description Due to a problem in the Intel® Quartus® Prime Pro Edition version 19.3, 10G/25G PTP variants of the E-tile Hard IP for Ethernet Intel® FPGA IP core, you may see the RX PTP Ready o_sl_rx_ptp_ready signal is not asserted when sending Ethernet packets after the reset and calibration sequence completes. Resolution A patch is available to fix this problem in the Intel® Quartus® Prime Pro Edition software version 19.3. Download and install the Patch from the appropriate link below. Download patch Intel® Quartus® Prime 19.3 Patch 0.02 for Windows(.exe) Download patch Intel® Quartus® Prime 19.3 Patch 0.02 for Linux(.run) Download the Readme for Intel® Quartus® Prime19.3 Patch 0.02(.txt) This problem has been fixed starting in the Intel® Quartus® Prime Pro Edition software version 19.4. Custom Fields values: ['novalue'] Troubleshooting 1409857017 False ['Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.4 19.3 ['Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']