Why does my Estimated Delay Added for Hold Timing report include a false path? - Why does my Estimated Delay Added for Hold Timing report include a false path? Description The Estimated Delay Added for Hold Timing report may include a false path because the fitter report is purely netlist-driven. It can't differentiate between multiple timing paths on the same connection. If a hold time critical path shares a common section with the path that has been set as a false path, both paths are considered delay-added paths by the fitter. The top 100 paths will show up in the report. Resolution It is safe to ignore the false paths in the Estimated Delay Added for Hold Timing Details section of the fitter report. Custom Fields values: ['novalue'] Troubleshooting 1409141403 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] No plan to fix 18.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']