Why do I see a “rx_dpa_hold” pin when “RX SOFT-CDR” mode is selected in the Stratix® 10 FPGA LVDS SERDES IP? - Why do I see a “rx_dpa_hold” pin when “RX SOFT-CDR” mode is selected in the Stratix® 10 FPGA LVDS SERDES IP? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3 and above, you can generate and compile a design with the Intel® Stratix® 10 FPGA LVDS SERDES IP with the rx_dpa_hold pin when the RX SOFT-CDR mode is selected. Resolution You may ignore the rx_dpa_hold pin and leave it unconnected. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15010575247 False ['LVDS SERDES IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 21.3 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']