Why do I see hold time violations in the Low Latency 40G Ethernet Intel® FPGA IP core when KR4 is enabled? - Why do I see hold time violations in the Low Latency 40G Ethernet Intel® FPGA IP core when KR4 is enabled?
Description Due to a problem with the Low Latency 40G Ethernet Intel® FPGA IP core on Intel® Stratix® 10 FPGA, you might see minor hold time violations when the KR4 feature is enabled. Resolution A possible temporary work around for this timing problem is to run seed sweeps so that better timing results are found. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Software.
Custom Fields values:
['novalue']
Troubleshooting
FB: 555465;
True
['Low Latency 40G Ethernet IP for Arria® 10 and Stratix® V']
['FPGA Dev Tools Quartus® Prime Software Pro']
18.0.1
17.1
['Stratix® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2023-01-10
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