Why is the parameter “Use core PLL reference clock connection” not available in the PHYLite IP Parameter Editor? - Why is the parameter “Use core PLL reference clock connection” not available in the PHYLite IP Parameter Editor?
Description Starting with the Quartus® Prime software version 17.0, the PHYLite IP does not support core PLL reference clock connection. The PHYLite PLL reference clock must be connected to a dedicated reference clock pin.
Custom Fields values:
['novalue']
Troubleshooting
FB: 439881;
False
['PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP']
['FPGA Dev Tools Quartus® Prime Software Pro']
17.0
16.1
['Arria® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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