IP Compiler for PCI Express SDC Constraint Generates Warnings - IP Compiler for PCI Express SDC Constraint Generates Warnings Description The following SDC constraint in the automatically generated Synopsys Design Constraints ( .sdc ) file for the IP Compiler for PCI Express generates warning messages: set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hissi_pcie_hip* }] Resolution This issue has no workaround. You can ignore the warning messages this constraint generates. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']