Why is the external loopback test failing for the 1x17.160G PCS Direct mode (System PLL Clocking) Example Design of the GTS PMA/FEC Direct PHY IP? - Why is the external loopback test failing for the 1x17.160G PCS Direct mode (System PLL Clocking) Example Design of the GTS PMA/FEC Direct PHY IP? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3.1, the 17.160G PCS direct mode (System PLL Clocking) Example Design provided with the GTS PMA/FEC Direct PHY IP shows intermittent failures for external loopback testing. To fix this, locate the file testwrap_rsfec_direct.sv in the Example Design project directory and modify the following statement from: assign tx_parallel_data[i*pld_max_data_width +: pld_max_data_width] = {tx_parallel_user_data[(i*80)+79],pulse_wire,tx_parallel_user_data[(i*80)+77 : (i*80)+0]}; To: assign tx_parallel_data[i*pld_max_data_width +: pld_max_data_width] =(o_rx_pcs_fully_aligned==1) ? {tx_parallel_user_data[(i*80)+79],tx_parallel_user_data[(i*80)+78],tx_parallel_user_data[(i*80)+77 : (i*80)+0]} :{1'b1,pulse_wire,tx_parallel_user_data[(i*80)+77 : (i*80)+39],data_valid,tx_parallel_user_data[(i*80)+37 : (i*80)+10],8'h1e,2'b01}; This problem is limited to only this configuration of the Example Design. Resolution This problem is planned to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16026079270 True ['IP Examples'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 24.3.1 ['Agilex™ 5 FPGA E-Series'] ['novalue'] ['novalue'] ['novalue']