Why are the RREF pins identified as GND pins in the pinout (.pin) file for Stratix V, Arria V and Cyclone V device families even though I am using a PLL? - Why are the RREF pins identified as GND pins in the pinout (.pin) file for Stratix V, Arria V and Cyclone V device families even though I am using a PLL? Description The pinout file (<project name>.pin) created by the Quartus® II software incorrectly identifies the RREF pins as GND pins in Stratix® V, Arria® V and Cyclone® V device families even though a PLL is used in your design. The RREF pins must be connected to GND on your PCB through a precision 2K Ohm resistors as specified in the Pin Connection Guidelines. Custom Fields values: ['novalue'] Troubleshooting novalue False ['PLL'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']