Why does the Triple-Speed Ethernet Stratix® 10 FPGA IP Design Example hardware test fail when using the Quartus® Prime Pro Edition Software Version 24.2? - Why does the Triple-Speed Ethernet Stratix® 10 FPGA IP Design Example hardware test fail when using the Quartus® Prime Pro Edition Software Version 24.2? Description Due to a problem the reset connected to the Triple-Speed Ethernet Stratix® 10 FPGA IP Design Example JTAG module being incorrectly connected as active low when it should be active high in the 10/100/1000Mb Ethernet MAC (Fifoless) Design Examples with the 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver. Snapshot from the System Console: Resolution There is no workaround to this problem in the Quartus® Prime Pro Edition Software Version 24.2. This problem is scheduled to be fixed in the future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16024446362 True ['Triple-Speed Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.2 ['Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['Stratix® 10 TX FPGA Signal Integrity Dev Kit']