Does the Stratix 10 hard memory controller support 2T timing for the address/command bus? - Does the Stratix 10 hard memory controller support 2T timing for the address/command bus? Description The Stratix® 10 hard memory controller operates at 1T timing for the address/command bus. It doesn't have the option to select 2T timing. Resolution If 2T timing for the address/command bus is required, choose the PHY-only option in the Stratix 10 EMIF IP Editor and develop your own custom controller. Note that calibration is always performed assuming 1T timing, which is safe for both 1T or 2T operations subsequently. Custom Fields values: ['novalue'] Troubleshooting FB: 466370; False ['External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.1 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']