Why might I see an incorrect frequency PreSICE transceiver calibration clock on Stratix® 10 devices? - Why might I see an incorrect frequency PreSICE transceiver calibration clock on Stratix® 10 devices? Description You might see an incorrect frequency PreSICE transceiver calibration clock on Stratix® 10 devices if the Quartus® Prime Software has cached an old version of your OSC_CLK_1 Quartus Settings File (QSF) assignment. A PLL inside the FPGA receives the clock from the OSC_CLK_1 pin and provides a 250-MHz calibration clock to PreSICE. This clock calibrates all Stratix® 10 L-Tile and H-Tile device ATX PLLs, fPLLs, CDR/CMU PLLs, and PMAs. The clock source and frequency are chosen in the Quartus® Prime Software project Device and Pin Option GUI or in the QSF file example assignment below. set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHz If you have recently changed your Configuration Clock Source setting in the Quartus® Prime Software, an old version may be cached and used by the Quartus® Prime Software. This can result in an incorrect frequency calibration clock which may result in a higher Bit Error Rate (BER) on your Stratix® 10 L-Tile or H-Tile device transceiver channel. Resolution To work around this problem you can clean your Quartus® Prime Software database after you have changed your Configuration Clock Source setting. You can do this using the Quartus® Prime Software menus as shown below. Project > Clean Project > All Revisions You must then recompile your Quartus® Prime Software project. Custom Fields values: ['novalue'] Troubleshooting 18013555188 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 20.3 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']