Extra gaps are inserted at RX in SerialLite III Continuous Mode - Extra gaps are inserted at RX in SerialLite III Continuous Mode Description Extra gaps might be inserted in Standard Clocking Mode (SCM), when Source/TX sends data to RX continuously without any data-valid gap, the Sink/RX interface could still de-assert data-valid to the user logic. Resolution To work around this problem a buffering scheme could be implemented to store some words first before forwarding a received packet. This problem is scheduled to be fixed in a future release of the Quartus® Prime software. Custom Fields values: ['novalue'] Troubleshooting 432032 True ['Serial Lite III Streaming IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']