Why does the Quartus® II software fail to fit more than four groups of 40G BaseKR IP into one side of a Intel® Stratix® V device? - Why does the Quartus® II software fail to fit more than four groups of 40G BaseKR IP into one side of a Intel® Stratix® V device? Description When you place more than four groups of 40G BaseKR IP on one side of a Stratix® V device, you might get the following error message: Error (175001): Could not place fractional PLL Error (177012): Route from the fractional PLL feedback output to the fractional PLL is congested This error is due to fPLL feedback clock congestion which is caused by the fPLL needing extra routing resources for reference clock compensation. Resolution To work around this problem, you can change your PLL compensation mode to "Direct Compensation" mode by adding the following line to your Quartus® II Settings File (.qsf) file. set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to *| |alt_e40_pma_sv_kr4:GEN_40BIT_PMA_SV.GEN_KR4_SV.pma|altera_pll_156M~FRACTIONAL_PLL This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software Custom Fields values: ['novalue'] Troubleshooting 1506794823 False ['novalue'] ['novalue'] novalue novalue ['Stratix® V GS FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']