What could be a reason why my Agilex™ 7 FPGA and SoC FPGA M-Series design fails when integrating an instance of the GPIO IP in bidirectional DDIO register mode? - What could be a reason why my Agilex™ 7 FPGA and SoC FPGA M-Series design fails when integrating an instance of the GPIO IP in bidirectional DDIO register mode? Description One of the possible reasons that an Agilex™ 7 FPGA and SoC FPGA M-Series design that includes a GPIO IP in bidirectional DDIO register mode fails is because of not use either the full input/output port or uses only part of the input/output port. The failure signatures can be in the form of an Internal Error, like below. *** Fatal Error: Segment Violation: faulting address=0x1, PC=0x7ffff03e3f7f : 0x7ffff03e3f7f: db_cdb_atom!CDB_ATOM_FANOUT_ITERATOR<true>::CDB_ATOM_FANOUT_ITERATOR(CDB_ATOM_OTERM const*, CDB_TRAVERSE) + 0x2f Module: quartus_fit Or a Compilation Error Message Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_1_0 Error(12274): A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid and the Fitter must be restarted. Resolution When using GPIO IP in bidirectional DDIO register mode, please use the input/output port to avoid errors. Custom Fields values: ['novalue'] Troubleshooting 22021206001 False ['GPIO IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 25.1 ['Agilex™ 7 FPGA M-Series'] ['novalue'] ['novalue'] ['novalue']