Error (175006): There is no routing connectivity between the clock tree and destination UFIND4H_UIB - Error (175006): There is no routing connectivity between the clock tree and destination UFIND4H_UIB Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.0, this error may be seen in an Intel Stratix® 10 MX design with the top and bottom HBM2 interfaces connected to the same core clock. Resolution Use a separate core clock for each HBM2 interface. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 545901 False ['High Bandwidth Memory (HBM2) Interface IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 18.0 ['Stratix® 10 MX FPGA'] ['novalue'] ['novalue'] ['novalue']