Why is my Qsys UniPHY based memory controller missing the pin_assignments.tcl file and other support files? - Why is my Qsys UniPHY based memory controller missing the pin_assignments.tcl file and other support files? Description A known issue exists with multiple instantiations of the same UniPHY-based memory controller in a Qsys system. The Qsys optimization step only creates the pin_assignments.tcl file and other support files for the original controller and reuses these files for all other instances of the same controller. Resolution The workaround is to make a trivial change to a non-critical parameter in the UniPHY core so that Qsys will recognize the core as unique and will generate all the appropriate files. The simplest change is to modify one of the board skew parameters in the Board Settings tab by 0.001ps. For example, change the "Maximum CK delay to DIMM/device" from 0.6ns to 0.599ns. Once you make all instances of the UniPHY controller unique, regenerate the Qsys system, and each instance should have its own set of files. Custom Fields values: ['novalue'] Troubleshooting 2205713210 False ['DDR3 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']