Having problem with CYCLONE V SX HPS side DDR3 Layout - Having problem with CYCLONE V SX HPS side DDR3 Layout Hi, We are using same SOC as Cyclone v SOC development Kit but 8GB DDR3 on HPS side. We have even kept layout almost same as that of SOC Development Kit HPS side DDR3. But when I get the SI Analysis Done using Hyperlynx, I find lot of noise on Address lines on my board design which I do not see on the CYCLONE V SOC Development kit. This happens when we observe the output of simulation on the DIE and not on the PINs with all address lines toggling together. This happens on my board but this does not happen on CYCLONE V SOC board. Can some one please help in this??? Replies: Re: Having problem with CYCLONE V SX HPS side DDR3 Layout Hi Calvin, There was some mistake in my SI simulation, my board is fine and is working well. Thanks a ton for support. Regards. Replies: Re: Having problem with CYCLONE V SX HPS side DDR3 Layout Hi Mhada, Kindly check the 'Cyclone V and Arria V SoC Device Design Guidelines' link below. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an-cv-av-soc-ddg.pdf Hope this will be helpful for you. Thank you. Replies: Re: Having problem with CYCLONE V SX HPS side DDR3 Layout When I say noise means a lot of ringing on 7 to 8 address lines in particular which is not there in SI analysis of SOC development board. In both cases we see the output on the die