Why is the F-Tile CPRI PHY Intel® FPGA IP in the generated design example not resetting properly after FPGA configuration? - Why is the F-Tile CPRI PHY Intel® FPGA IP in the generated design example not resetting properly after FPGA configuration? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, there is a problem in the RTL codes of the F-Tile CPRI PHY Intel® FPGA IP Design Example file cpriphy_ftile_hw.v . The reset status signal ninit_done from the Reset Release Intel® FPGA IP is not connected to the F-Tile CPRI PHY Intel FPGA IP reset ports. Hence, the reset signal does not take effect during the hardware run. Resolution You can add the ninit_done and init_done signal to i_reconfig_reset, i_rest_n, i_tx_rst_n and i_rx_rst_n in cpriphy_ftile_hw.v file under the dut_wrapper module . .i_reconfig_reset (i_reconfig_reset | ninit_done), //active high .i_rst_n (i_rst_n[cpriphy_inst] & init_done ), .i_tx_rst_n (i_tx_rst_n[cpriphy_inst] & init_done ), .i_rx_rst_n (i_rx_rst_n[cpriphy_inst] & init_done ), This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.4. Custom Fields values: ['novalue'] Troubleshooting 15011847433 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.4 22.3 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']