Why is the minimum phase shift step in my rtl simulation different from the board level measurement? - Why is the minimum phase shift step in my rtl simulation different from the board level measurement? Description The minimum phase shift step in your RTL simulation and actual board will be different if you are using an incorrect phase shift step resolution value in the ALTPLL Megawizard™. This option will only be available if you checked the "enable phase shift step resolution edit" in the Dynamic Phase Configuration option box. If the value you put in phase shift step resolution is lower than the actual minimum phase shift step specification, the Quartus® II software will generate incorrect data for RTL simulation. The minimum phase shift step resolution can be determined by calculation. Please refer to: Phase-Locked Loop (ALTPLL) Megafunction User Guide (PDF) , in the Dynamic Phase Reconfiguration Chapter. From this user guide, the finest phase shift step is 1/8th of the PLL's VCO frequency. If you don't know the minimum phase shift step of current device and want Quartus II software to determine the minimum phase shift step automatically, please uncheck the "enable phase shift step resolution edit" the in Dynamic Phase Configuration option box. Related Articles Why is the phase shift resolution for the ALTPLL megafunction in RTL simulation different than the expected value? Why are the dynamic phase steps not matching the phase shift resolution in RTL simulation for Cyclone III devices? Custom Fields values: ['novalue'] Troubleshooting novalue False ['PLL'] ['novalue'] novalue novalue ['Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']