Why does the Intel® Quartus® Prime Timing Analyzer ignore clocks with a period greater than 2147483ns? - Why does the Intel® Quartus® Prime Timing Analyzer ignore clocks with a period greater than 2147483ns? Description Due to the integer limit in the Intel® Quartus® Prime Pro and Standard Edition software, you may see that clocks created with a period greater than 2147483ns is ignored. Constraint: create_clock -name clkA -period 2147484 [get_ports clk] Warning: Ignored create_clock: Time value "2147484" is not valid Ignored create_clock: Option -period: Invalid clock period Resolution To work around this limitation, use a clock period equal to or smaller than 2147483 ns. The size of the period variable is 32 bits ranging from −2147483648ps to 2147483647ps. The create_clock constraint accepts values in nanoseconds by default but stores them as picoseconds. Therefore, 2147484ns is stored as 2147484000ps, which exceeds the limit of a 32-bit integer. Custom Fields values: ['novalue'] Troubleshooting FB: 578220; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']