How do I update the multicast hash table of the Triple Speed Ethernet IP core? - How do I update the multicast hash table of the Triple Speed Ethernet IP core? Description As an example, assume you want the IP core to accept packets with a destination address of 01-1C-23-17-4A-CB. The IP core represents these address bits [47:0] in reverse order as shown below. Address bits 7:0 = 0x01 -> Hash Code bit 0 (XOR MAC address 7:0) = “1” Address bits 15:8 = 0x1C -> Hash Code bit 1 (XOR MAC address 15:8) = “1” Address bits 23:16 = 0x23 -> Hash Code bit 2 (XOR MAC address 23:16) = “1” Address bits 31:24 = 0x17 -> Hash Code bit 3 (XOR MAC address 31:24) = “0” Address bits 39:32 = 0x4A -> Hash Code bit 4 (XOR MAC address 39:32) = “1” Address bits 47:40 = 0xCB -> Hash Code bit 5 (XOR MAC address 47:40) = “1” Therefore the hash code for this example is 0x37. To accept packets with this address, set bit 0 of the MultiCast Hash Table configuration register at "DWord offset" 0x77 (0x40 0x37) to the value of 1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Ethernet'] ['novalue'] novalue novalue ['Arria® GX FPGA', 'Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® FPGAs', 'Cyclone® II FPGAs', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'MAX® 10 10 FPGAs', 'MAX® II CPLDs', 'MAX® II Z CPLD', 'MAX® V CPLDs', 'Stratix® FPGAs', 'Stratix® GX FPGA', 'Stratix® II FPGAs', 'Stratix® II GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']