Warning(13469): Verilog HDL assignment warning at mbl_table_mux.sv(116): truncated value with size 24 to match size of target (23) - Warning(13469): Verilog HDL assignment warning at mbl_table_mux.sv(116): truncated value with size 24 to match size of target (23) Description This warning might be seen in the Intel® Quartus® Prime Pro Edition Software version 23.3 when you compile a design containing the Memory Subsystem Intel® FPGA IP that instantiates a Content-Addressable Memory Intel® FPGA IP using the MBL algorithm. It happens when a Content-Addressable Memory Intel® FPGA IP instance using MBL is connected to an external memory that is not large enough to hold both hash and key/result tables. Resolution This warning cannot be ignored. To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 23.3, perform one of the following solutions: Lower the log2 number of the key/result table Increase the size of your memory device Reduce key/result width Lower the number of bins per row This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14020205512 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 23.3 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']