RLDRAM II Controller with UniPHY Simulation fails in Riviera-PRO - RLDRAM II Controller with UniPHY Simulation fails in Riviera-PRO Description Simulation in Riviera-PRO may fail, with an error message suggesting that MEM_WRITE_DQS_WIDTH must contain a positive value. Resolution The workaround for this issue is to open the alt_mem_if_rldramii_mem_model.sv file in a text editor, and make the following changes: Near the top of the file, change the parameter declaration for MEM_WRITE_DQS_WIDTH from: parameter MEM_WRITE_DQS_WIDTH = “”; to parameter MEM_WRITE_DQS_WIDTH = 1; Further down in the file, change: time [MEM_WRITE_DQS_WIDTH - 1:0] mem_dk_time; to time mem_dk_time[MEM_WRITE_DQS_WIDTH] Custom Fields values: ['novalue'] Troubleshooting novalue True ['Simulation'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']