Why do setup and minimum pulse width timing violations occur in the LVDS SERDES IP Design Example? - Why do setup and minimum pulse width timing violations occur in the LVDS SERDES IP Design Example?
Description Due to an issue in Quartus® Prime Pro Edition Software version 26.1 and earlier, you may encounter setup and minimum pulse width timing violations in the LVDS SERDES IP Design Example. This issue is caused by an incorrect value of the vco_data_rate_ratio parameter used in the LVDS SERDES IP, which leads to improper timing constraints and resulting violations. a { text-decoration: none; color: #464feb; } tr th, tr td { border: 1px solid #e6e6e6; } tr th { background-color: #f5f5f5; } Resolution To work around this issue, follow the steps below: Step 1: In the auto-generated file intel_lvds_core10_ph2_hw_ed_synth_intel_lvds_0_example_design_example_design_intel_lvds_core10_ph2_191_<string>.sv , Original: .vco_data_rate_ratio(0), Change to: .vco_data_rate_ratio(<correct_vco_data_rate_ratio>), Step 2: In the auto-generated file ed_synth_intel_lvds_0_example_design_example_design_intel_lvds_core10_ph2_191_<string>.sdc , add this SDC constraint set ip_params(vco_data_rate_ratio) <correct_vco_data_rate_ratio> Step 3: Re-compile the design The correct vco_data_rate_ratio parameter value based on the LVDS SERDES IP data rate (Mbps) shown in table below: Use the appropriate vco_data_rate_ratio based on the LVDS SERDES IP data rate: data_rate >= 600 Mbps 1 600 Mbps > data_rate >= 300 Mbps 2 data_rate < 300 Mbps 4 This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Related IP Core: LVDS SERDES IP
Custom Fields values:
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Troubleshooting
QS-51520
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['FPGA Dev Tools Quartus® Prime Software Pro']
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26.1
['Agilex™ 3 FPGAs and SoCs', 'Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGA Direct RF-Series', 'Agilex™ 9 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs']
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['novalue'] - 2026-04-29
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