Inefficient Memory Transactions For Quarter-rate Designs - Inefficient Memory Transactions For Quarter-rate Designs Description This problem affects DDR3 products. The HPC II memory controller might be unable to perform seamless back-to-back sequential read or write transactions in quarter-rate designs. Resolution The workaround for this issue is to modify the alt_mem_ddrx_controller.v file as described below. Open the alt_mem_ddrx_controller.v file in an editor and locate the following lines: localparam CFG_MAX_PENDING_RD_CMD = 16; localparam CFG_MAX_PENDING_WR_CMD = 8; In the above lines, change 16 to 32 and change 8 to 16. This issue will be fixed in a future release. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']