Why does the Agilex™ 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP not remove the HDM Base Address before the address conversion? - Why does the Agilex™ 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP not remove the HDM Base Address before the address conversion? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3 and earlier, the Agilex™ 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP doesn't remove the HDM Base Address, which causes the unexpected converted address in the user logic. For Example: 1. The transaction with HDM base address = 0x4f414c000000 and offset = 0, so the complete address should be 0x4f414c000000 + 0 = 0x4f414c000000; 2. The Agilex™ 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IPCXL IP outputs to user logic with converted address[51:6] = 0x13d0_5300_0000; 3. This converted address will not be routed to the target memory address 0, which causes unexpected behavior. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15013917193 False ['R-Tile for Compute Express Link Solution'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 23.2 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']