Why does the "o_rx_error" port of the E-Tile Hard IP for Ethernet Hard Intel® FPGA IP core not reflect oversized frames in transmission? - Why does the "o_rx_error" port of the E-Tile Hard IP for Ethernet Hard Intel® FPGA IP core not reflect oversized frames in transmission? Description Due to a fault in the 100G E-Tile Hard IP for Ethernet Hard Intel® FPGA IP core RX status detection logic, you might observe oversized frames ( default maximum frame size in IP setting is 1518), fail to cause the relative bit of port o_rx_error to assert to reflect oversized frame behavior. Resolution There is no plan to fix this issue in future IP release. You can use statistic register(0x924/0x925) to monitor whether there is oversized frame in transmission. Custom Fields values: ['novalue'] Errata 1509265467 False ['E-tile Hard IP for Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 21.1 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']