Cannot Simulate CPRI IP Core Auto-Rate Negotiation in Verilog HDL With ModelSim 6.4b or Later - Cannot Simulate CPRI IP Core Auto-Rate Negotiation in Verilog HDL With ModelSim 6.4b or Later Description CPRI MegaCore function variations with auto-rate negotiation enabled and with Verilog HDL output files cannot simulate successfully in the Mentor Graphics ModelSim 6.4b simulator or in later versions of this simulator. This issue affects all CPRI MegaCore function variations with auto-rate negotiation enabled and with Verilog HDL output files. Simulation cannot complete for these variations using these simulators. Resolution Use the ModelSim 6.4a simulation tool to simulate these variations. This issue is fixed in version 10.1 of the CPRI MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 10.1 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25