Why can't two center PLLs drive two different memory controllers with UniPHY at the bottom of a Stratix V device? - Why can't two center PLLs drive two different memory controllers with UniPHY at the bottom of a Stratix V device? Description The center PLLs at the bottom only have access to one PHYCLK network in the Stratix® V device. Resolution If you need to use center PLLs to drive two external memory interfaces, use the PLL sharing mode. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']