Agilex 5 GTS PMA/FEC Direct Loopback - Agilex 5 GTS PMA/FEC Direct Loopback Say I need to connect an oscillating component (with parallel data) to the GTS from the fabric, and then loop it back to via serial in fabric, and then read the output parallel data. To set this up, can I simply: 1: Set the "TX/RX Common PMA Options Loopback mode" to "parallel" 2: Route `i_rx_serial_data` back to `o_tx_serial_data` assign gts_i_rx_serial_data = gts_o_tx_serial_data; assign gts_i_rx_serial_data_n = gts_o_tx_serial_data_n; 3: Connect an oscillating component to the `rx_parallel_data`? Of course I have omitted many signals here, but is it along the right lines? Many thanks! Replies: Re: Agilex 5 GTS PMA/FEC Direct Loopback Hi, I believe that your initial question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Altera experts. Otherwise, the community users will continue to help you on this thread. Thank you very much. Replies: Re: Agilex 5 GTS PMA/FEC Direct Loopback Hi, Just following up to check if you have any further inquiries related to this topic that I can assist with. If everything has been addressed, I’m planning to close the case shortly. Please feel free to let me know if there's anything else you'd like to discuss. Thank you! Replies: Re: Agilex 5 GTS PMA/FEC Direct Loopback Hi, I noticed that there seems to be some issue with the image uploading. Just to clarify, I am referring to the PMA-transmitter-to-receiver parallel loopback (TX2RXPAR) as in the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs -> "Figure 21. PMA Loopback Modes". Sorry for the inconvenience. Replies: Re: Agilex 5 GTS PMA/FEC Direct Loopback Hi, Thanks for your update. Based on your description, it seems your datapath is structured as follows: Oscillator → tx_parallel_data input → GTS PHY → rx_parallel_data output → DMA → HPS To achieve this setup, you can enable the Parallel Loopback path (Path B). This configuration allows the parallel data fed into the TX interface to be directly routed to the RX interface, bypassing the serializer, deserializer, and CDR blocks. This approach should help simplify your testing or validation process without involving the full high-speed serial path. Let me know if you need further clarification or assistance. Best regards, Chee Pin Replies: Re: Agilex 5 GTS PMA/FEC Direct Loopback Hi @CheePin_C_Intel Yes let me explain a little more. My design will be: Oscillator -> GTS (loopback) -> DMA -> HPS. Where the oscillator produced parallel data, the GTS serialises it and loops it back deserialised, and the DMA fetches data for a user application. I really don't have a preference in terms of what loopback mode to use, it could be any of the three - likely I will try them all. Many thanks! Replies: Re: Agilex 5 GTS PMA/FEC Direct Loopback Hi, I understand you have some inquiries regarding the parallel loopback configuration of the XCVR PHY. To ensure we're aligned, could you kindly elaborate on the specific data flow of your target implementation? It would be helpful if you could reference Figure 21: PMA Loopback Modes in the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs , so we can better understand your intended setup and provide more accurate guidance. Looking forward to your clarification.