Why am I writing and reading back incorrect values when accessing the transceiver PMA and PCS registers within the Intel® Stratix® 10 Low Latency 40G Ethernet design example? - Why am I writing and reading back incorrect values when accessing the transceiver PMA and PCS registers within the Intel® Stratix® 10 Low Latency 40G Ethernet design example? Description Due to a problem in the Intel® Quartus® Prime Software version 18.1, writes to the transceiver PMA and PCS registers within the Intel® Stratix® 10 Low Latency 40G Ethernet design example will not take effect. In addition, reads from the transceiver PMA and PCS registers within the Intel Stratix 10 Low Latency 40G Ethernet design example will return incorrect values. Resolution This problem is fixed in the Intel Quartus Prime Software version 18.1.1. Custom Fields values: ['novalue'] Troubleshooting FB: 605315; False ['Low Latency 40G Ethernet IP for Arria® 10 and Stratix® V'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1.1 18.1 ['Stratix® 10 FPGAs and SoCs', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']