Possible Timing Failure on Certain Paths in Designs Targeting Cyclone V Devices - Possible Timing Failure on Certain Paths in Designs Targeting Cyclone V Devices Description This problem affects DDR2, DDR3, and LPDDR2 products. External memory interfaces targeting Cyclone V devices may exhibit timing failure on paths from the following nodes to the FPGA core: *if0|p0|umemphy|uio_pads|dq_ddio[*].ubidir_dq_dqs|altdq_dqs2_inst|input_path_gen[*].read_fifo~OUTPUT_DFF_* Resolution The workaround for this issue is as follows: Restrict the placement of core nodes to meet timing requirements. Compile the IP using multiple seeds and additional synthesis and fitter optimizations enabled. This issue will be fixed in a future version. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0.1 ['Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']