Why is the Read Device Dummy Clock instruction unreliable when using the QUAD and DUAL I/O options on the ASMI Parallel Intel® FPGA IP? - Why is the Read Device Dummy Clock instruction unreliable when using the QUAD and DUAL I/O options on the ASMI Parallel Intel® FPGA IP? Description When the read_dummyclk input of the ASMI Parallel Intel® FPGA IP is asserted, the IP performs a read of the non-volatile control register of the EPCQ configuration device to determine the number of dummy cycles that are required for a fast read operation. Due to a problem with the IP, the outputs of the FPGA are not tri-stated during the read status operation at the time when the EPCQ device should return the data. This leads to a conflict on the DATA[3..0] signals. This conflict may mean that the incorrect value is returned. Resolution Do not use the DUAL or QUAD I/O options available on the ASMI Parallel Intel® FPGA IP. This problem has been resolved in the the Quartus® II software version 14.0 and onwards. Related Articles How can I address known issues with the ALTASMI_PARALLEL megafunction in the Quartus II software version 13.1? Custom Fields values: ['novalue'] Troubleshooting 2205815199 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']